FastVeri™ (SystemC-based High-Speed Simulator) Product Overview

Drastically Accelerate Your System-Level Simulation!

In designing of digital system products and/or SoC (System on a Chip), co-verification of hardware/software design using virtual platform simulator becomes increasingly important to verify the entire system at early design stage. Conventionally, such co-simulation has been performed by connecting the instruction set simulator (ISS) and Register Transfer Level (RTL) simulation of the peripheral hardware. However, ISS based co-simulation is too slow to verify the entire system.

FastVeri converts software C source code into the SystemC(*1) model, which can simulate the software execution onto the target CPU with cycle-approximate accuracy. This can be realized by "instruction timing back-annotation method" developed at STARC(*2). The method embeds SystemC timing functions which reflects the instruction cycles into the original C source code with analyzing the target CPU assembly code. FastVeri also converts embedded C software code of peripheral IO/register access and the interrupt handler into the channel method access in SystemC. So that the generated CPU model can be easily connected with the transaction level hardware device SystemC models.

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	FastVeri at a glance

*1) SystemC is a new hardware-modeling language standardized by Open SystemC Initiative (OSCI) that was established in September 1999.

*2) Instruction timing back-annotation technology was developed by Semiconductor Technology Academic Research Center (STARC) and has been licensed to InterDesign Technologies.