InterDesign Technologies demonstrated our cutting edge Electronic System Level (ESL) design technology and tools at the recent 43rd Design Automation Conference, 24th- 27th July, San Francisco.

 

DAC Exhibition Overview

[Name of the Show] 43rd Desgin Automation Conference
[Dates/Hours] 7/24 (Mon) - 7/27 (Thu) 9:00 - 18:00 (- 13:00 on 7/27)
[Place] Moscone Center, San Francisco, CA (Booth #3154 and Suite #3237)
[Contents] Product Exhibition and Suite

Booth Exhibition

FastVeri : Fast hardware/software co-verification framework

InterDesign's solution for high-speed HW/SW co-verification, FastVeri is the Electronic System Level (ESL) tool, where over 100Mhz ultra high-speed target CPU simulation can be achieved. FastVeri converts software C source code into the SystemC model with "Instruction timing back-annotation technology". The generated CPU model simulates the software execution onto the target CPU with cycle-approximate accuracy. FastVeri supports ARM7, ARM9, ARM9E and now expanding to MIPS64.

Further information is available at http://www.interdesigntech.co.jp/english/fastveri

Please visit InterDesign's booth #3154 and check the outstanding features of boosting the simulation speed.

Private Demos available !!

Our private suite room will be opened in booth #3237. Please ask and register for our private demonstration to
sales@interdesigntech.co.jp

Our suite was full of visitors and successful. Thank you!

Topic A : High-Speed Hardware/Software Co-Verification with FastVeri

We demonstrated the detailed technology of high-speed co-simulation with FastVeri and its application case studies. Presentation shows 2 topics :"Software testing with SystemC virtual platform simulator" : We create the platform model by FastVeri and run the virtual platform simulation with 3rd vendor’s SystemC debugger as Summit Design's Vista SystemC IDE. This environment enables software designers to test and debug their embedded software source code. "FastVeri applies on Hardware verification" : We shows FastVeri application cases on hardware design and verification flow which combine FastVeri High-speed CPU model with HDL simulator/emulator or behavioral synthesis tool.

Topic B : System-level design exploration with SER

We demonstrated a new ESL design tool named SER which embodies system-level design specification, exploration and refinement.
SER accepts algorithmic specification models written in C and it enables interactive system-level design space exploration with HW/SW partitioning, network topology design, bus protocol selection and bus interface synthesis. SER generates transaction level platform models which can be combined with FastVeri's high-speed co-simulation framework and which enables performance analysis and software testing with the virtual platform simulator. In addition, SER generates C model descriptions for a backend behavioral synthesis tool.
SER provides a consistent and powerful methodology and tool chain from a top-level specification model all the way down to RTL design.
*SER is developed by the Center for Embedded Computer Systems (CECS) at the University of California, Irvine and the Japan Aerospace Exploration Agency (JAXA) in cooperation with InterDesign Technologies.

5th Annual NASCUG (North American SystemC Users Meeting)

We gave a presentation related to FastVeri high-speed HW/SW co-verification at NASCUG co-located with DAC’06.
Monday, July 24, 2006, Room 200, Moscone Center
2:00 pm - 6:00 pm (reception starts at 5:00 pm)
Information is available at http://www.nascug.org

Presentation Title
"High-Speed Hardware/Software Co-Verification with CPU Model Generator from Software Code"
Dai Araki : InterDesign Technologies Inc.
Noriyoshi Ito : Semiconductor Technology Academic Research Center (STARC)
Takao Shinsha : Applistar Corporation
Yoshikazu Mori : Oki Network LSI Co.,Ltd.